X40430 Datasheet, PDF (7/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430/X40431 – Preliminary Information
Figure 6. V_TRIP Set/Reset Sequence (X = 1, 2, 3)
V_TRIPX Programming
No
Desired
V_TRIPX
Present Value
YES
Execute
V_TRIP Reset Sequence
New V_X applied =
Old V_X applied + Error
NO
Execute
Set Higher V_TRIP Sequence
Execute
Set Higher V_X Sequence
Apply V_CC and Voltage
Desired V_TRIPX to V_X
Decrease V_X
New V_X applied =
Old V_X applied - Error
Execute Reset V_TRIPX
Sequence
Error < -MDE
Output Switches?
YES
Actual V_{TRIPX –}
Desired ^VTRIPX
Error < | MDE |
DONE
Error > +MDE
Vx = V_CC, V2MON, V3MON
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
REV 1.2.3 11/28/00
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Characteristics subject to change without notice. 7 of 24