X40430 Datasheet, PDF (14/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430/X40431 – Preliminary Information
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 16. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
Slave
t
Address
o
A
A
A
p
C
C
C
K
K
K
1
A
C
K
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
REV 1.2.3 11/28/00
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Characteristics subject to change without notice. 14 of 24