X40430 Datasheet, PDF (2/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I²C bus.
The device utilizes Xicor’s proprietary Direct Write^™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
X40430
14-Pin SOIC, TSSOP
V2FAIL 1
V2MON ₂
LOWLINE 3
NC 4
14 V_CC
13 WDO
12 V3FAIL
11 V3MON
MR 5
RESET 6
V_{SS 7}
10 WP
9 SCL
8 SDA
X40431
14-Pin SOIC, TSSOP
V2FAIL 1
V2MON ₂
LOWLINE 3
NC 4
14 ^VCC
13 WDO
12 V3FAIL
11 V3MON
MR 5
RESET ₆
V_{SS 7}
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V_TRIP2 and
goes HIGH when V2MON exceeds V_TRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the V_TRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V_SS or V_CC
when not used.
3 LOWLINE Early Low V_CC Detect. This CMOS output signal goes LOW when V_CC < V_TRIP1 and goes high
when V_CC > V_TRIP1.
4
NC
No connect.
5
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t_PURST thereafter.
6 RESET/ RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever
RESET
V_CC falls below V_TRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t_PURST) on power up. It will also stay active until manual reset is released
and for t_PURST thereafter.
RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
V_CC falls below V_TRIP voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t_PURST) on power up. It will also stay active until manual reset is released
and for t_PURST thereafter.
7
V_SS
Ground
REV 1.2.3 11/28/00
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Characteristics subject to change without notice. 2 of 24