X40430 Datasheet, PDF (18/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430/X40431 – Preliminary Information
WP Pin Timing
SCL
SDA IN
WP
START
t_SU:WP
Clk 1
Slave Address Byte
Clk 9
t_HD:WP
Write Cycle Timing
SCL
SDA
8^th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
t_WC⁽¹⁾
Parameter
Write Cycle Time
Min.
Typ.
Max.
Unit
5
10
ms
Note: (1) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
V_TRIPX
V_CC
V2MON or
V3MON
LOWLINE or
t_R
V2FAIL or
V3FAIL
X = 2, 3
t_RPDL
t_RPDX
V_RVALID
t_RPDL
t_RPDX
t_RPDL
t_RPDX
t_F
REV 1.2.3 11/28/00
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Characteristics subject to change without notice. 18 of 24