X40430 Datasheet, PDF (5/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40430/X40431 – Preliminary Information
Figure 3. V_TRIPX Set/Reset Conditions
V_TRIPX
(X = 1, 2, 3)
V_CC/V2MON/V3MON
WDO
SCL
0
70
V_P
70
7
SDA
A0h
00h
t_WC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40430/
31 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Timer Start
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE
The X40430 is shipped with standard V1, V2 and V3
threshold (V_TRIP1, V_TRIP2, V_TRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a V_TRIPx Voltage (x=1, 2, 3)
There are two procedures used to set the threshold
voltages (V_TRIPx), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V_TRIPx is 2.9 V and the new
V_TRIPx is 3.2 V, the new voltage can be stored directly
into the V_TRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the V_TRIPx voltage before setting the new value.
Setting a Higher V_TRIPx Voltage (x=1, 2, 3)
To set a V_TRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V_TRIPx threshold voltage to the corre-
sponding input pin (Vcc(V1MON), V2MON or V3MON).
The Vcc(V1MON), V2MON and V3MON must be tied
together during this sequence. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 01h for V_TRIP1, 09h for V_TRIP2, and 0Dh for
V_TRIP3, and a 00h Data Byte in order to program
V_TRIPx. The STOP bit following a valid write operation
initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation
REV 1.2.3 11/28/00
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Characteristics subject to change without notice. 5 of 24