W964B6BBN Datasheet, PDF (9/30 Pages) Winbond – 1M WORD X 16BIT LOW POWER PSEUDO SRAM

W964B6BBN
AC Characteristics
(Under Recommended Operating Conditions unless otherwise noted)
Read Operation
PARAMETER
Read Cycle Time
Chip Enable Access Time
Output Enable Access Time
Address Access Time
Output Data Hold Time
SYM.
tRC
tCE
tOE
tAA
tOH
-70
Min. Max.
70
-
-
65
-
40
-
65
5
-
-80
Min. Max.
80
-
-
75
-
45
-
75
5
-
CE1 Low to Output Low-Z
tCLZ
5
-
5
-
OE Low to Output Low-Z
tOLZ
0
-
0
-
CE1 High to Output High-Z
tCHZ
-
20
-
25
OE High to Output High-Z
tOHZ
-
20
-
25
Address Setup Time to CE1 Low
Address Setup Time to OE Low
tASC
-5
-
-5
-
tASO
30
-
35
-
tASO[ABS]
10
-
10
-
LB / UB Setup Time to CE1 Low
tBSC
-5
-
-5
-
LB / UB Setup Time to OE Low
Address Invalid Time
tBSO
10
-
10
-
tAX
-
5
-
5
Address Hold Time from CE1 Low
tCLAH
70
-
80
-
Address Hold Time from OE Low
tOLAH
40
-
45
-
Address Hold Time from CE1 High
tCHAH
-5
-
-5
-
Address Hold Time from OE High
tOHAH
-5
-
-5
-
LB / UB Hold Time from CE1 High
tCHBH
-5
-
-5
-
LB / UB Hold Time from OE High
tOHBH
-5
-
-5
-
CE1 Low to OE Low Delay Time
tCLOL
25 1000 30 1000
OE Low to CE1 High Delay Time
tOLCH
35
-
40
-
CE1 High Pulse Width
OE High Pulse Width
tCP
12
-
15
-
tOP
25 1000 30 1000
tOP[ABS]
12
-
15
-
UNIT NOTES
nS
nS *1, *3
nS
*1
nS
*1
nS
*1
nS
*2
nS
*2
nS
*2
nS
*2
nS
*4
nS *3, *5
nS
*6
nS
nS
nS
nS
nS
*9
nS
nS
nS
nS
nS *3, *5, *7, *8
nS
*7
nS
nS *5, *7, *8
ns
*6
Publication Release Date: March 31, 2003
-9-
Revision A1