W964B6BBN Datasheet, PDF (8/30 Pages) Winbond – 1M WORD X 16BIT LOW POWER PSEUDO SRAM

W964B6BBN
Capacitance
Test conditions: TA = 25°C, f = 1.0 MHz
SYMBOL
DESCRIPTION
CIN1 Address Input Capacitance
CIN2 Control Input Capacitance
CIO Data Input/Output Capacitance
TEST SETUP
VIN _{= 0V}
VIN _{= 0V}
VIO _{= 0V}
TYP.
-
-
-
MAX.
5
5
8
UNIT
pF
pF
pF
DC Characteristics
(Under Recommended Operating Conditions unless otherwise noted)
notes*1, *2, *3
PARAMETER
SYM.
TEST CONDITIONS
MIN. MAX. UNIT
Input Leakage Current
ILI VIN = VSS to VDD
-1.0 +1.0 µA
Output Leakage Current
ILO VOUT = VSS to VDD, Output Disable -1.0 +1.0 µA
Output High Voltage
Level
VOH VDD = VDD, IOH = -0.5 mA
1.8
-
V
Output Low Voltage Level VOL IOL = 1 mA
-
0.4
V
(TTL)
IDDS
VDD ₌ VDD Max.,
VIN _{= VIH or VIL}
-
3
mA
Standby
CE1 = CE2 = VIH
Current
VDD = VDD Max.,
(CMOS) IDDS1 ^{VIN ≤ 0.2V or VIN ≥ VDD -0.2V,}
-
CE1 = CE2 ≥ VDD -0.2V
Active Current
IDDA1
IDDA2
VDD = VDD Max.,
VIN = VIH or VIL,
CE1= VIL and CE2 =
VIH_, IOUT = 0 mA
tRC / tWC =
Minimum
-
tRC / tWC =
1 µS
-
70 µA
20 mA
3
mA
Notes:
*1: All voltages are reference to VSS.
*2: DC Characteristics are measured after following POWER-UP timing.
*3: IOUT depends on the output load conditions.
-8-