W964B6BBN Datasheet, PDF (17/30 Pages) Winbond – 1M WORD X 16BIT LOW POWER PSEUDO SRAM

W964B6BBN
Timing Waveforms, Continued
Read Timing #3 (Address Access after OE Control Access)
ADDRESS
CE1
OE
LB / UB
DQ
(Output)
tRC
ADDRESS VALID
tASO
tOLAH
tAX
tOE
tBSO
tOLZ
tOH
tRC
ADDRESS VALID
tAA
tOHAH
tOHZ
tOHBH
tOH
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
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Publication Release Date: March 31, 2003
Revision A1