W39V080A Datasheet, PDF (9/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V080A
GPI Register Table
BIT
7−5
4
3
2
1
0
FUNCTION
Reserved
Read GPI4 pin status
Read GPI3 pin status
Read GPI2 pin status
Read GPI1 pin status
Read GPI0 pin status
Product Identification Registers
There is a software method to read out the Product Identification in both the Programmer interface
mode and the LPC interface mode. Thus, the programming equipment can automatically matches the
device with its proper erase and programming algorithms.
In the full-chip(8Mb) LPC interface mode, a read from FFBC, 0000(hex) can output the manufacturer
code, DA(hex). A read from FFBC, 0001(hex) can output the device code D0(hex).
For dual-BIOS(4Mbx2) LPC mode , a read from FFBC, 0000(hex) can output the manufacturer code,
DA(hex). A read from FFBC,0001(hex) can output the device code 90(hex).
In the software access mode, a JEDEC 3-byte command sequence can be used to access the
product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer
code, DA(hex). A read from address 0001(hex) outputs sequence or an alternate one-byte command
sequence (see Command Definition table for detail).the device code, D0(hex).” The product ID
operation can be terminated by a three-byte command.
Identification Input Pins ID[3:0]
These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot
device should be 0000b. And all the subsequent parts should use the up-count strapping.
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M
system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS
storage space, the ID[2:1] pins are inverted in the ROM and are compared to address lines [21:20].
ID[3] can be used as like active low chip-select pin.
The 32Mbit address space is as below:
BLOCK
LOCK
ADDRESS RANGE
4M Byte BIOS ROM
None
FFFF, FFFFh: FFC0, 0000h
The ROM responds to top 1M byte pages based on the ID pins strapping according to the following
table:
ID[2:1] PINS
00x
01x
10x
11x
ROM BASED ADDRESS RANGE
FFFF, FFFFh: FFF0, 0000h
FFEF, FFFFh: FEF0, 0000h
FFDF, FFFFh: FFD0, 0000h
FFCF, FFFFh: FFC0, 0000h
Publication Release Date: Dec. 28, 2005
-9-
Revision A4