W39V080A Datasheet, PDF (8/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V080A
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100 　S, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively
erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls
within a protected sector, DQ6 toggles for about 1 μS after the program command sequence is
written, and then returns to reading array data.
Reading Toggle Bits DQ6
Whenever the system initially starts to read toggle bit status, it must read DQ7-DQ0 at least twice in a
row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the
value of the toggle bit after the first read. While after the second read, the system would compare the
new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ7-DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is
high, the system should then determine again whether the toggle bit is toggling or not, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not
completed the operation, and the system must write the reset command to return to reading array
data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5 through successive read cycles, and
determines the status as described in the previous paragraph. Alternatively, the system may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
while it returns to determine the status of the operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the
device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must hardware reset to return to the read mode.
REGISTER
There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the GPI[4:0] pins on the W39V080A.This is a pass-through register which can read
via memory address FFBC0100(hex), or FFBxE100(hex). Since it is pass-through register, there is no
default value.
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