W39V080A Datasheet, PDF (11/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V080A
8. TABLE OF COMMAND DEFINITION
COMMAND
NO. OF 1^ST CYCLE 2^ND CYCLE 3^RD CYCLE 4^TH CYCLE 5^TH CYCLE 6^TH CYCLE
DESCRIPTION Cycles (1) Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read
Sector Erase
1
A_IN D_OUT
6
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA⁽⁵⁾ 30
Byte Program
4
5555 AA 2AAA 55 5555 A0 A_IN D_IN
Product ID Entry
3
5555 AA 2AAA 55 5555 90
Product ID Exit ⁽⁴⁾
3
5555 AA 2AAA 55 5555 F0
Product ID Exit ⁽⁴⁾
1
XXXX F0
Notes:
1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[19:11]
3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = FXXXXh for Unique Sector15 (Boot Sector)
SA = 7XXXXh for Unique Sector7
SA = EXXXXh for Unique Sector14
SA = 6XXXXh for Unique Sector6
SA = DXXXXh for Unique Sector13
SA = 5XXXXh for Unique Sector5
SA = CXXXXh for Unique Sector12
SA = 4XXXXh for Unique Sector4
SA = BXXXXh for Unique Sector11
SA = 3XXXXh for Unique Sector3
SA = AXXXXh for Unique Sector10
SA = 2XXXXh for Unique Sector2
SA = 9XXXXh for Unique Sector9
SA = 1XXXXh for Unique Sector1
SA = 8XXXXh for Unique Sector8
SA = 0XXXXh for Unique Sector0
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Publication Release Date: Dec. 28, 2005
Revision A4