W39V080A Datasheet, PDF (26/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Timing Waveforms, for LPC Interface Mode, continued
14.3 Program Cycle Timing Diagram
W39V080A
CLK
#RESET
#LFRAME
LAD[3:0]
Memory
Write
1st Start Cycle
0000b 011Xb
1 Clock 1 Clock
XXXXb
XXXXb
Address
XXXXb
XXXXb
X101b
0101b
Load Address "5555" in 8 Clocks
0101b
Data
TAR
Sync
0101b
1010b
1010b 1111b Tri-State 0000b
Load Data "AA" in 2 Clocks 2 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAME
LAD[3:0]
Memory
Write
2nd Start Cycle
0000b 011Xb
1 Clock 1 Clock
XXXXb
XXXXb
Address
Data
XXXXb
XXXXb
X010b
1010b
1010b
1010b
0101b
0101b
Load Address "2AAA" in 8 Clocks
Load Data "55"
in 2 Clocks
Write the 2nd command to the device in LPC mode.
TAR
Sync
1111b Tri-State 0000b
2 Clocks
1 Clock
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAME
LAD[3:0]
Memory
Write
3rd Start Cycle
0000b 011Xb
1 Clock 1 Clock
XXXXb
XXXXb
Address
Data
XXXXb
XXXXb
X101b
0101b
0101b
0101b
0000b
1010b
Load Address "5555" in 8 Clocks
Load Data "A0"
in 2 Clocks
Write the 3rd command to the device in LPC mode.
TAR
Sync
1111b Tri-State 0000b
2 Clocks
1 Clock
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAME
LAD[3:0]
Memory
Write
4th Start Cycle
Address
0000b 011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
A[15:12]
1 Clock 1 Clock
Load Ain in 8 Clocks
A[11:8]
A[7:4]
Data
TAR
Sync
A[3:0]
D[3:0]
D[7:4]
1111b Tri-State 0000b
Load Din in 2 Clocks
2 Clocks
1 Clock
Internal
program start
TAR
Internal
program start
Write the 4th command(target location to be programmed) to the device in LPC mode.
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