W39V080A Datasheet, PDF (4/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V080A
3. PIN CONFIGURATIONS
NC
1
NC
2
NC
3
V SS
MODE
4
5
A10(GPI4)
6
R/#C(CLK)
7
VDD
8
Vpp
9
#RESET
10
A9(GPI3)
11
A8(GPI2)
12
A7(GPI1)
13
A6(GPI0)
14
A5(#WP)
15
A4(#TBL)
16
32L STSOP
32
#OE(#INIT)
31
30
29
28
27
26
25
24
23
#WE(#LFRAME)
RY/#BY(RSV)
DQ7(U/#L)
DQ6(D/#F)
DQ5(RSV)
DQ4(RSV)
DQ3(LAD3)
V SS
DQ2(LAD2)
22 DQ1(LAD1)
21
DQ0(LAD0)
20
A0(ID0)
19
A1(ID1)
18
A2(ID2)
17
A3(ID3)
A7(GPI1)
A6(GPI0)
A5(#WP)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)
DQ0(LAD0)
RA
A
8
^
G
P
I
2
v
A
9
G^
P
I
3
v
#
R
E
S
E
T
VV
PD
PD
/
#
C
^
C
L
K
v
1
0
^
G
P
I
4
v
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9 _{32L PLCC} 25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
MODE
VSS
NC
NC
VDD
#OE(#INIT)
#WE(#LFRAME)
RY/#BY(RSV)
DQ7(U/#L)
DD _VDD D D
QQ _S QQ Q Q
12 S3 4 5 6
^^
^^ ^ ^
LL
L RRD
AA
ASS /
DD D V V #
12
3vvF
vv
v
v
NC
1
MODE
2
NC
3
NC
4
NC
5
NC
6
A10(GPI4)
7
NC
CLK
8
9
VDD
10
Vpp
11
#RESET
12
NC
13
NC
14
A9(GPI3)
15
A8(GPI2)
16
A7(GPI1)
17
A6(GPI0)
18
A5(#WP) 19
A4(#TBL) 20
40L TSOP
40
VSS
39
VDD
38
#WE(#LFRAME)
37
#OE(#INIT)
36
RY/#BY(RSV)
35
DQ7(U/#L)
34
DQ6(D/#F)
33
DQ5(RSV)
32
DQ4(RSV)
31
VDD
30
VSS
29
VSS
28 DQ3(LAD3)
27 DQ2(LAD2)
26 DQ1(LAD1)
25 DQ0(LAD0)
24 A0(ID0)
23 A1(ID1)
22 A2(ID2)
21 A3(ID3)
4. BLOCK DIAGRAM
#WP
#TBL
CLK
LAD[3:0]
#LFRAME
MODE
#INIT
#RESET
LPC
Interface
64K BYTES BLOCK 15
64K BYTES BLOCK 14
64K BYTES BLOCK 13
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
RY/#BY
Program-
mer
Interface
64K BYTES BLOCK 2
64K BYTES BLOCK 1
64K BYTES BLOCK 0
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
5. PIN DESCRIPTION
SYM.
MODE
#RESET
#INIT
#TBL
#WP
CLK
GPI[4:0]
INTERFACE
PGM LPC
*
*
*
*
*
*
*
*
*
ID[3:0]
*
LAD[3:0]
*
#LFRAME
*
D/#F
*
U/#L
*
R/#C
*
A[10:0]
*
DQ[7:0] *
#OE
*
#WE
*
RY/#BY *
VDD
*
*
VSS
*
*
RSV
*
*
NC
*
*
PIN NAME
Interface Mode Selection
Reset
Initialize
Top Boot Block Lock
Write Protect
CLK Input
General Purpose Inputs
Identification Inputs
Pull Down with Internal Resistors
Address/Data Inputs
LPC Cycle Initial
Dual Bios/Full Chip
Pull Down with Internal Resistors
Upper 4M/Lower 4M
Pull Down with Internal Resistors
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Ready/Busy
Power Supply
Ground
Reserve Pins
No Connection
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