W39V080A Datasheet, PDF (27/34 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Timing Waveforms for LPC Interface Mode, continued
14.4 #DATA Polling Timing Diagram
W39V080A
CLK
#RESET
#LFRAME
LAD[3:0]
CLK
#RESET
#LFRAME
LAD[3:0]
CLK
#RESET
#LFRAME
LAD[3:0]
Memory
Write
1st Start Cycle
Address
Data
TAR
Sync
0000b 011Xb
A[31:28] A[27:24] A[23:20] A[19:16] An[15:12] An[11:8] An[7:4]
An[3:0] Dn[3:0] Dn[7:4] 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn"
in 2 Clocks
2 Clocks
Write the last command(program or erase) to the device in LPC mode.
1 Clock
Start next
command
0000b
1 Clock
Start
Memory
Read
Cycle
0000b _010Xb XXXXb
XXXXb
Address
XXXXb ^An[19:16]
An[15:12] An[11:8]
An[7:4]
An[3:0]
TAR
Sync
1111b Tri-State 0000b
Data
XXXXb Dn7,xxx
TAR
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks 1 Clock Data out 2 Clocks
Read the DQ7 to see if the internal write complete or not.
Next Start
0000b
1 Clock
Start
0000b
Memory
Read
Cycle
010Xb An[31:28]
An[27:24]
An[23:20]
Address
An[19:16] An[15:12]
An[11:8]
An[7:4]
An[3:0]
TAR
Sync
1111b Tri-State 0000b
Data
XXXXb Dn7,xxx
TAR
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks 1 Clock Data out 2 Clocks
When internal write complete, the DQ7 will equal to Dn7.
Next Start
0000b
1 Clock
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Publication Release Date: Dec. 28, 2005
Revision A4