W28F641B Datasheet, PDF (9/31 Pages) Winbond – 64MBIT (4MBIT × 16) PAGE MODE DUAL WORK FLASH MEMORY

W28F641B/T
[A21-A0]
000088H
000085H
000084H
Customer Programmable Area
Factory Programmed Area
000081H
000080H
Reserved for Future Implementation
(DQ15-DQ2)
Customer programmable Area Lock Bit (DQ1)
Factory programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)
Table 5. Bus Operations ^{(1, 2)}
MODE
Read Array
Output Disable
Standby
Reset
Read Identifier
Codes/OTP
Read Query
Write
NOTE #RESET #CE #OE #WE ADDRESS V_PP DQ0 − 15
6
V_IH
V_IL
V_IL
V_IH
X
X
DOUT
V_IH
V_IL
V_IH
V_IH
X
X
High Z
V_IH
V_IH
X
X
X
X
High Z
3
V_IL
X
X
X
X
X
High Z
6
V_IH
V_IL
V_IL
V_IH
See
Table 3, 4
X
See
Table 3, 4
6,7
V_IH
V_IL
V_IL
V_IH
See
Appendix
X
See
Appendix
4,5,6
V_IH
V_IL
V_IH
V_IL
X
X
DIN
Notes:
1. Refer to DC Characteristics. When V_PP ≤ V_PPLK, memory contents can be read, but cannot be altered.
2. X can be V_IL or V_IH for control pins and addresses, and V_PPLK or V_PPH1/2 for V_PP. See DC Characteristics for V_PPLK and V_PPH1/2
voltages.
3. #RESET at V_SS ±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when V_PP = V_PPH1/2 and
V_DD = 2.7V to 3.6V.
Command writes involving full chip erase are reliably executed when V_PP = V_PPH1 and V_DD = 2.7V to 3.6V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold #OE low and #WE low at the same timing.
7. Refer to Appendix for more information about query code.
Publication Release Date: March 27, 2003
-9-
Revision A3