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W28F641B Datasheet, PDF (20/31 Pages) Winbond – 64MBIT (4MBIT × 16) PAGE MODE DUAL WORK FLASH MEMORY
W28F641B/T
AC Characteristics - Read-only Operations(1)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYM.
MIN. MAX. UNIT
Read Cycle Time
tAVAV
80
nS
Address to Output Delay
tAVQV
80
nS
#CE to Output Delay (note 3)
tELQV
80
nS
Page Address Access Time
tAPA
35
nS
#OE to Output Delay (note 3)
tGLQV
20
nS
#RESET High to Output Delay
tPHQV
150
nS
#CE or #OE to Output in High Z, whichever Occurs First (note 2)
tEHQZ, tGHQZ,
20
nS
#CE to Output in Low Z (note 2)
tELQX
0
nS
#OE to Output in Low Z (note 2)
tGLQX
0
nS
Output Hold from first Occurring Address, #CE or #OE Change
(note 2)
tOH
0
nS
Address Setup to #CE, #OE, Going Low for Reading Status
Register (note 4,6)
tAVEL, tAVGL
10
nS
Address Hold from #CE, #OE, Going Low for Reading Status
Register (note 5,6)
tELAX, tGLAX
30
nS
#CE, #OE Pulse Width High for Reading Status Register (note 6) tEHEL, tGHGL 30
nS
Notes:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact to tELQV.
4. Address setup time (tAVEL to tAVGL) is defined from the falling edge of #CE or #OE (whichever goes low last).
5. Address hold time (tELAX to tGLAX) is defined from the falling edge of #CE or #OE (whichever goes low last).
6. Specifications tAVEL, tAVGL, tELAX, tGLAX, and tEHEL,, tGHGL for read operations apply to only status register read operations.
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