W28F641B Datasheet, PDF (19/31 Pages) Winbond – 64MBIT (4MBIT × 16) PAGE MODE DUAL WORK FLASH MEMORY

W28F641B/T
DC Characteristics, continued
PARAMETER
SYM.
TEST
CONDITIONS
V_DD = 2.7V − 3.6V
UNIT
Min. Typ. Max.
Input Low Voltage (note 5)
V_IL
Input High Voltage (note 5)
V_IH
-0.4
0.4 V
2.4
V_DDQ
+0.4
V
Output Low Voltage (note 5)
Output High Voltage (note 5)
V_PP Lockout during Normal Operations
(note 3, 5, 6)
V_OL
V_OH
V_PPLK
V_DD = V_DD Min., V_DDQ =
V_DDQ Min., IOL = 100 µA
V_DD = V_DD Min., V_DDQ =
V_DDQ Min., IOH = -100 µA
V_DDQ
-0.2
0.2 V
V
0.4 V
V_PP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations (note 6)
V_PPH1
1.65 3.0
3.6 V
V_PP during Block Erase, (Page Buffer)
Program or OTP Program Operations
(note 6)
V_PPH2
11.7
12
12.3 V
V_DD Lockout Voltage
V_LKO
1.5
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V_DD = 3.0V and TA = +25° C unless
V_DD is specified.
2. I_CCWS and I_CCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase
suspend mode, the device's current draw is the sum of I_CCES and I_CCR or I_CCW. If read is executed while in (page buffer)
program suspend mode, the device’s current draw is the sum of I_CCWS and I_CCR.
3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when V_PP ≤ V_PPLK, and not guaranteed in
the range between V_PPLK (max.) and V_PPH1 (min.), between V_PPH1 (max.) and V_PPH2 (min.) and above V_PPH2 (max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.
Standard address access timings (tAVQV) provide new data when address are changed.
5. Sampled, not 100% tested.
6. V_PP is not used for power supply pin. With V_PP ≤ V_PPLK, block erase, full chip erase, (page buffer) program and OTP program
cannot be executed and should not be attempted.
Applying 12V ±0.3V to V V_PP provides fast erasing or fast programming mode. In this mode, V_PP is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and
layout considerations given to the V_DD power bus.
Applying 12V ±0.3V to V_PP during erase/program can only be done for a maximum of 1,000 cycles on each block. V_PP may be
connected to 12V ±0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
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Publication Release Date: March 27, 2003
Revision A3