W972GG6JB Datasheet, PDF (85/87 Pages) Winbond – 16M  8 BANKS  16 BIT DDR2 SDRAM

W972GG6JB
10.31 Clock frequency change in precharge Power Down mode
T0
T1
T2
T4
CLK
CLK
CMD
CKE
NOP
NOP
TX
TX+1
TY
TY+1
TY+2
TY+3
TY+4
Tz
NOP
NOP
DLL
RESET
NOP
Valid
ODT
tIS
tRP
tAOFD
Frequency change
Occurs here
tIS
tXP
200 Clocks
tIH
ODT is off during
DLL RESET
Minimum 2 clocks
required before
changing frequency
Stable new clock
before power down exit
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Publication Release Date: Nov. 29, 2011
Revision A02