W83194BR-645 Datasheet, PDF (7/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
5.5 Power Management Pins
PIN
PIN NAME TYPE
DESCRIPTION
PD#*
IN Power Down pin, if PD# = 0, all clocks are stopped.
Power good input signal comes from ACPI with high active. This
33
VTT_PWGD
IN
3.3V input is level sensitive strobe used to determine FS [4:0]
and MULTISEL input are valid and is ready to sample. This pin
is high active.
45
CPU_STOP#*
IN
CPU clock stop control pin, This pin is low active. Internal
120KΩ pull-up.
12
PCI_STOP#*
IN
PCI clock stop control pin, This pin is low active. Internal 120KΩ
pull-up.
5.6 Power Pins
PIN
1
11
36
42
29
13,19
48
28
5, 8, 18, 24, 25,
32, 37, 41, 46
PIN NAME
VDDR
VDDZ
VDDA
VDDC
VDDAGP
VDDPCI
VDDSD
VDD48
GND
DESCRIPTION
Power supply for REF0: 2 3.3V.
Power supply for ZCLK 3.3V.
Power supply for core logic. 3.3V
Power supply for CPUCLK 3.3V.
Power supply for AGP outputs.
Power supply for PCI outputs.
Power supply for SDRAM 3.3V.
Power supply for 48/24 MHz outputs.
Circuit Ground.
Publication Release Date: April 13, 2005
-5-
Revision 2.1