W83194BR-645 Datasheet, PDF (13/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
7.3 Register 6 PCI Clock Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD
7
15
1 PCICLK_F1
6
14
1 PCICLK_F0
5
23
1 PCICLK 5
4
22
1 PCICLK 4
3
21
1 PCICLK 3
2
20
1 PCICLK 2
1
17
1 PCICLK 1
0
16
1 PCICLK 0
DESCRIPTION
7.4 Register 7 48 MHz, ZCLK, REF Clock Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD
DESCRIPTION
7
27
1 48 MHz
6
26
1 24_48 MHz
24/48 MHz frequency control
5
SEL_24
1 1: 24 MHz.
0: 48 MHz.
4
10
1 ZCLK1
3
9
1 ZCLK0
2
4
1 REF2
1
3
1 REF1
0
2
1 REF0
7.5 Register 8: AGP Control Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD
DESCRIPTION
CPUCLKT/C0 Stop control: 0: CPUCLK0 free run
7
1
1: CPUCLK0 can stopped by CPU_STOP#
CPUCLKT/C1 Stop control: 0: CPUCLK1 free run
6
1
1: CPUCLK1 can stopped by CPU_STOP#
5
0 PCI_F0 Stop control: 0: PCI_F0 free run
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Publication Release Date: April 13, 2005
Revision 2.1