W83194BR-645 Datasheet, PDF (11/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
7. I²C CONTROL AND STATUS REGISTERS
The Register 0~3 are reserved for external clock buffer
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 4: Frequency Select Register (default = 0)
BIT
NAME
PWD
DESCRIPTION
7
SSEL [3]
0
6
SSEL [2]
0 _{Frequency selection by software via I2C}
5
SSEL [1]
0
4
SSEL [0]
0
Enable software program FS [4:0].
3
EN_SSEL
0 0 = Select frequency by hardware.
1= Select frequency by software I²C - Bit 4: 7, 2.
2
SSEL [4]
0 Frequency selection bit 4
Enable Spread Spectrum in the frequency table.
1
EN_SPSP
0 0 = Normal
1 = Spread Spectrum enabled
Enable reload safe frequency when the watchdog is timeout.
0 EN_SAFE_FREQ 0 0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 9 bit 4~0.
7.2 Register 5: CPU, SDRAM Clock Register (1 = Enable, 0 = Stopped)
BIT
PIN NO.
PWD
DESCRIPTION
7
47
1 SDRAM
6
44, 43
1 CPUCLKT/C1
5
40, 39
1 CPUCLKT/C0
4
15
X FS [4] Read back.
3
14
X FS [3] Read back
2
4
X FS [2] Read back
1
3
X FS [1] Read back
0
2
X FS [0] Read back
Publication Release Date: April 13, 2005
-9-
Revision 2.1