W83194BR-645 Datasheet, PDF (17/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
0 SP_DOWN [0] 1 Spread Spectrum Down Counter bit 0
7.11 Register 14: Divisor and Step-less Enable Control Register
BIT
NAME
7 EN_MN_PROG
6 RATIO_SEL [4]
5 RATIO_SEL [3]
4 RATIO_SEL [2]
3 RATIO_SEL [1]
2 RATIO_SEL [0]
1
TEST0
0
Reserved
PWD
0
1
0
0
1
1
0
0
DESCRIPTION
0: use frequency table
1: use M/N register to program frequency
The equation is VCO freq. = 14.318MHz * (N+4)/ M.
When the watchdog timer is timeout, this will be clear.
In this time, the frequency is set to hardware default
latched or safe frequency set by EN_SFAE_FREQ
(Register 9 bit 0).
CPU, PCI, AGP, SDRAM, and ZCLK ratio selection. The ratio is
shown as following table.
Test bit 0. Winbond test bit, do not change them.
7.12 Register 15: CPU_ZCLK Skew Control Register
BIT
NAME
PWD
DESCRIPTION
7 CPU_ZCLK_SKEW [2]
1 CPU to ZCLK SKEW control
6
Reserved
0 Reserved
5
Reserved
1
4
Reserved
0
3
Reserved
2
Reserved
0
Reserved
1
1
Reserved
1
0
Reserved
1
7.13 Register 16: CPU_AGP_SKEW
BIT
NAME
PWD
DESCRIPTION
7
Reserved
6
Reserved
0
Reserved for Winbond internal use, do not change them
0
5
Reserved
0 Reserved for Winbond internal use, do not change them
4
CPU_STOP
1 CPU_STOP pin read back
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Publication Release Date: April 13, 2005
Revision 2.1