W83194BR-645 Datasheet, PDF (15/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
Register 8: AGP Control Register (1 = Enable, 0 = Stopped), continued
BIT
PIN NO. PWD
DESCRIPTION
PCI_F1 Stop control: 0: PCI_F1 free run
4
0
1: PCI_F1 can stopped by PCI_STOP#
3
30
1 AGP_1
2
31
1 AGP_0
1 MULTISEL0 1 MULTISEL0 trapping pin data read back
0 MULTISEL1 0 MULTISEL1 (IREF output control)
7.6 Register 9: Watchdog Control Register
BIT
NAME
PWD
DESCRIPTION
7
Reserved
0 Reserved
Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.
6
EN_WD
0 Read this bit will return a counting state. If timer continues down count,
this bit will return 1. Otherwise, this bit will return 0.
Watchdog Timeout Status. If the watchdog is started and timer down
5 WD_TIMEOUT 0 counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to
1, when the watchdog is restart in the next time. This bit is Read Only.
4 SAF_FREQ [4] 0
3 SAF_FREQ [3] 0
2
SAF_FREQ [2]
0
Watchdog safe frequency bits. These bits will be reloaded into FS
[4:0], if the watchdog is timeout and enable reload safe frequency bits.
1 SAF_FREQ [1] 0
0 SAF_FREQ [0] 0
7.7 Register 10: Watchdog Timer Register
BIT
NAME
PWD
DESCRIPTION
7 WD_TIME [7] 0 Watchdog timeout time. The bit resolution is 250 mS. The default time
6
WD_TIME [6]
0
is 8*250 mS = 2.0 seconds. If the watchdog timer is start, this register
will be down count. Read this register will return a down count value.
5 WD_TIME [5] 0
4 WD_TIME [4] 0
3 WD_TIME [3] 1
2 WD_TIME [2] 0
1 WD_TIME [1] 0
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Publication Release Date: April 13, 2005
Revision 2.1