W83194BR-645 Datasheet, PDF (6/24 Pages) Winbond – CLOCK GENERATOR FOR SIS 645/650 CHIPSET

W83194BR-645
31, 30
9, 10
AGPCLK [0:1] OUT AGP clock outputs for AGP.
ZCLK [0:1] OUT Z clock outputs for chipset.
5.3 I2C Control Interface
PIN
PIN NAME TYPE
DESCRIPTION
34
SDATA*
I/O
Serial data of I²C 2-wire control interface, Internal 120kΩ pull-
up.
35
SDCLK*
IN
Serial clock of I²C 2-wire control interface, Internal 120kΩ pull-
up.
5.4 Fixed Frequency Outputs
PIN
PIN NAME TYPE
DESCRIPTION
Deciding the reference current for the CPUCLK pairs. The pin
was connected to the precision resistor tied to ground to decide
38
IREF
IN the appropriate current. There are two modes to select different
current via power on trapping the Pin 26 (MULTISEL0). The
table is show as follows.
REF0
OUT 3.3V, 14.318 MHz reference clock output.
2
FS0&
IN_td120k
Latched input for FS0 at initial power up for H/W selecting the
output frequency. Internal 120KΩ pull-down.
REF1
OUT 3.3V, 14.318 MHz reference clock output.
3
FS1&
IN_td120k
Latched input for FS1 at initial power up for H/W selecting the
output frequency, Internal 120KΩ pull-down.
REF2
OUT 3.3V, 14.318 MHz reference clock output.
4
FS2&
IN_td120k
Latched input for FS2 at initial power up for H/W selecting the
output frequency. Internal 120KΩ pull-down.
24_48 MHz OUT 24 MHz or 48 MHz selected by Register.
26
MULTISEL0*
IN_tp120k
MULTISEL0 at initial power up for H/W selecting the current
multiplier for CPU outputs. Internal 120KΩ pull-up.
27
48 MHz OUT 48 MHz output for USB.
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