W741E260 Datasheet, PDF (55/94 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

W741E260
Instruction Set Table 2, continued
CLR EVF, #I
Clear EVent Flag
Machine Code:
Machine Cycle:
Operation:
Description:
01000000
I7 I6 I5 I4 I3 I2 I1 I0
1
Clear event flag
The condition corresponding to the data specified by I7 to I0 is controlled.
I0~I7 Mode after execution of instruction
I0 = 1 EVF0 caused by overflow from the divider 0 is reset.
I1 = 1
I2 = 1
EVF1 caused by underflow from the timer 0 is reset.
EVF2 caused by the signal change at port RC is reset.
I3
Reserved
I4 = 1
EVF4 caused by overflow from the divider 1 is reset for W741C260 body;
EVF4 caused by the falling edge signal on INT pin is reset for W741C250 body.
I5 & I6 Reserved
I7 = 1 EVF7 caused by underflow from the timer 1 is reset.
CLR PSR0
Machine Code:
Machine Cycle:
Operation:
Description:
CLR WDT
Machine Code:
Machine Cycle:
Operation:
Description:
Clear Port Status Register 0 (RC port signal change flag)
01000010
1
00000000
Clear Port Status Register 0 (RC port signal change flag)
When this instruction is executed, the RC port signal change flag (PSR0) is
cleared.
Reset the last 4 bits of the WatchDog Timer
00010111
10000000
1
Reset the last 4 bits of the watchdog timer
When this instruction is executed, the last 4 bits of the watchdog timer are
reset.
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Publication Release Date: March 1998
Revision A2