W741E260 Datasheet, PDF (22/94 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

W741E260
Interrupts
The W741E260 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and
one external interrupt source (port RC) for W741C260 body or three internal interrupt sources (Divider
0, Timer 0, Timer 1) and two external interrupt sources ( port RC, INT pin) for W741C250 body.
Vector addresses for each of the interrupts are located in the range of program memory (ROM)
addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF
is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an
interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or
MOV IEF, #I instruction is invoked. The interrupts can also be disabled by executing the DIS INT
instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily
and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt
subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 11. The
control diagram is shown below.
Divider 0
overflow signal
Timer 0
underflow signal
Port RC
signal change
Divider 1
overflow signal
Timer 1
underflow
signal
SQ
R
SQ
R
SQ
R
SQ
R
SQ
R
EN INT
MOV IEF, #I
EVF.0
Initial Reset
IEF.0
EVF.1
IEF.1
EVF.2
IEF.2
EVF.4
IEF.4
EVF.7
IEF.7
Enable
Interrupt
Process
Circuit
Interrupt
Vector
Generator
004H
008H
00CH
014H
020H
Initial Reset
Disable
CLR EVF, #I instruction
DIS INT instruction
Figure 10. Interrupt Event Control Diagram
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or
EN INT is executed again. Otherwise, these interrupts can be disabled by executing DIS INT
instruction. The bit descriptions are as follows:
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