W741E260 Datasheet, PDF (13/94 Pages) Winbond – 4-BIT FLASH MICROCONTROLLER

W741E260
Fosc
Divider0
... Q1 Q2
Q9 Q10 Q11 Q12 Q13 Q14
RRRR
S
EVF.0
Q
R
HEF.0
IEF.0
Hold mode release (HCF.0)
Divider0 interrupt (INT0)
PMF.3
Fosc/16384
Fosc/1024
Enable
/Disable
Mask Option
1. Reset
2. CLR EVF, #01H
3. CLR DIVR0
WDT
Qw1 Qw2 Qw3 Qw4
R
R
R
R
Overflow signal
System Reset
1. Reset
2. CLR WDT
Figure 5. Organization of Divider0 and Watchdog Timer
Parameter Flag (PMF)
The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by
the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:
3210
PMF _W
Note: W means write only.
Bit 0, Bit1, Bit2 Reserved
Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.
= 1 The fundamental frequency of the watchdog timer is FOSC/16384.
Timer/Counter
1. Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L
(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),
the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event
flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops
operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1
has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting
MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0
is shown in Figure 6.
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Publication Release Date: March 1998
Revision A2