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W83781D Datasheet, PDF (51/53 Pages) Winbond – MONITORING IC
ISA Read/Write Timing
PARAMETER
Valid Address to Read Active
Valid Address to Write Active
Data Hold
Data Setup
Address Hold from Inactive Read
Read Cycle Update
Read Strobe Width
Read Data Hold
Read Strobe to Clear IRQ
Active Read to Valid Data
Address Hold from Inactive Write
Write Cycle Update
Write Strobe to Clear IRQ
Write Strobe Width
Read Cycle = tAR + tRD+tRCV
Write Cycle = tAW+tWR - tWCV
W83781D
PRELIMINARY
SYMBOL
t-AR
tAW
tDH
tDS
tRA
tRCU
tRD
tRDH
tRI
tRVD
tWA
tWCU
tWI
tWR
RC
WC
MIN.
10
10
5
80
40
200
120
40
5
80
120
210
210
MAX.
60
115
60
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
9.2.3 Serial Bus Timing Diagram
SCL
SDA IN
t HD;SDA
SDA OUT
t SCL
t HD;DAT
VALID DATA
t SU;DAT
t SU;STO
Serial Bus Timing Diagram
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Publication Release Date : Nov. 1997
Revision 0.60