W83781D Datasheet, PDF (14/53 Pages) Winbond – MONITORING IC

W83781D
PRELIMINARY
7.1.1 The first serial bus access timing are shown as follow:
(a) Serial bus write to internal address register followed by the data byte
0
SCL
780
78
SDA
0 1 0 1 1 0 1 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
Frame 1
Serial Bus Address Byte
Ack
Ack
by
Frame 2
by
781D
781D
Internal Index Register Byte
0
SCL (Continued)
78
SDA (Continued)
D7 D6 D5 D4 D3 D2 D1 D0
Frame 3
Data Byte
Ack
by
781D
Stop
by
Master
Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0
SCL
780
78
SDA
0 1 0 1 1 0 1 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
Frame 1
Serial Bus Address Byte
Ack Stop by
Ack
by
781D
Frame 2
Internal Index Register Byte
by
781D
Master
0
Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
SCL
780
78
SDA
0 1 0 1 1 0 1 R/W
D7 D6 D5 D4 D3 D2 D1 D0
Start By
Master
Frame 1
Serial Bus Address Byte
Ack
by
Frame 2
Ack
by
Master
Stop by
Master
781D
Internal Index Register Byte
0
Serial Bus Write to Internal Address Register Only
-9-
Publication Release Date : Nov. 1997
Revision 0.60