W9864G6JT Datasheet, PDF (5/42 Pages) Winbond – 1M  4 BANKS  16 BITS SDRAM

W9864G6JT
5. BALL DESCRIPTION
BALL LOCATION BALL NAME FUNCTION
DESCRIPTION
H7, H8, J8, J7, J3,
J2, H3, H2, H1,
G3, H9, G2
A0A11
Address
Multiplexed pins for row and column address.
Row address: A0A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
G7, G8
BS0, BS1
Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch time.
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
DQ0DQ15
Data
Multiplexed pins for data output and input.
Input/ Output
Disable or enable the command decoder. When
G9
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
F8
RAS
Row Address
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
F7
CAS
Column Address
Strobe
Referred to RAS
F9
WE
Write Enable _{Referred to RAS}
F1, E8
F2
F3
A9, E7, J9
A1, E3, J1
A7, B3, C7, D3
A3, B7, C3, D7
E2, G1
UDQM,
LDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside
DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection.
Publication Release Date: Dec. 23, 2011
-5-
Revision A01