W9864G6JT Datasheet, PDF (15/42 Pages) Winbond – 1M  4 BANKS  16 BITS SDRAM

W9864G6JT
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V  0.3V, TA = 0 to 70°C for -6, TA = -40 to 85°C for -6I/-6A, TA / TCASE = -40 to 105°C for -6K) (Notes: 5, 6)
PARAMETER
-6/-6I/-6A
-6K
SYM.
UNIT NOTES
MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command Period
tRC
Active to Precharge Command Period
tRAS
Active to Read/Write Command Delay Time
tRCD
Read/Write(a) to Read/Write(b)Command Period tCCD
Precharge to Active(b) Command Period
tRP
Active(a) to Active(b) Command Period
tRRD
Write Recovery Time
CL* = 2
tWR
CL* = 3
60
60
42 100000 42 100000 nS
15
18
1
1
tCK
15
18
nS
12
12
2
2
tCK
2
2
CLK Cycle Time
CLK High Level Width
CLK Low Level Width
Access Time from CLK
CL* = 2
7.5 1000 7.5 1000
tCK
CL* = 3
6 1000 6 1000
tCH
2
2
8
tCL
2
2
8
CL* = 2
6
6
tAC
9
CL* = 3
5
5
Output Data Hold Time
tOH
3
9
Output Data High Impedance Time
tHZ
6
6
7
Output Data Low Impedance Time
tLZ
0
0
9
Power Down Mode Entry Time
tSB
6
6
nS
Transition Time of CLK (Rise and Fall)
tT
1
1
Data-in-Set-up Time
tDS
1.5
1.5
8
Data-in Hold Time
tDH
1
1
8
Address Set-up Time
tAS
1.5
1.5
8
Address Hold Time
tAH
1
1
8
CKE Set-up Time
tCKS
1.5
1.5
8
CKE Hold Time
tCKH
1
1
8
Command Set-up Time
tCMS
1.5
1.5
8
Command Hold Time
tCMH
1
1
8
Refresh Time
-40°C ≤ TA / TCASE ≤ 85°C t_REF
64
64
mS
(4K/Refresh Cycles) 85°C < TA / TCASE ≤ 105°C _tREFA
--
16
mS
Mode Register Set Cycle Time
tRSC
2
2
tCK
Exit self refresh to ACTIVE command
tXSR
72
72
nS
*CL = CAS Latency
* -- = not support
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Publication Release Date: Dec. 23, 2011
Revision A01