W925E625 Datasheet, PDF (49/75 Pages) Winbond – 8-bit CID MICROCONTROLLER

W925E/C625
FSK TRANSIMT CONTROL REGISTER
Bit:
7
6
5
4
FTE FTM FDS
-
Mnemonic: FSKTC
(initial=00H)
3
2
1
0
-
-
LO1 LO0
Address: C6h
FTE: FSK transmit Enable. Enable=1, Disable=0
FTM: FSK signal Standard. Bellcore 202=1, V.23=0
FDS: FSK data sending status
LO0, LO1: FSK transmit level option
FSK output level
LO1
LO0
150Mv
0
0
120Mv
0
1
95Mv
1
0
75Mv
1
1
FSK TRANSMIT DATA BUFFER
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
FSKTB.7 FSKTB.6 FSKTB.5 FSKTB.4 FSKTB.3 FSKTB.2 FSKTB.1 FSKTB.0
Mnemonic: FSKTB
Address: C7h
FSKTB.0: Only This bit will be latched and send out as FSK signal
When FTE enable will set the FDS to high to enable the internal latch clock in 1200Hz. When FDS is
in high state, FSKTB bit0 will be sent out by FSK modulator at the rising edge of latch clock. FDS
could be cleared by software to inform no more data will be sent out after the last bit is sent
completely. If the FDS is cleared then FTE will become low at next rising latch clock to disable FSK
modulator and clear FDS by hardware automatically.
When FTE is set, FSK modulation flag (FSF) will be set at every rising edge of latch clock to produce
an interrupt shared with CID interrupt routine. If a CID interrupt occurs, user can check FSF to know if
this interrupt is caused by FSK modulator. The only way to stop FSK signal immediately is to disable
FTE by software.
6.13 I/O Ports
There are six 8-bit ports named from P0 to P4 in W925E/C625. All ports can be configured as input or
output mode. Except P0, every port has pull high resistor enable/disable by PxH register. After reset
the initial state of each port is in input mode and the value of the registers from P0 to P3 are FFh. The
I/O port is described as below:
P0: I/O mode is controlled by P0IO. Only P0 output as open drain mode and without pull high
resistor.
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Publication Release Date: July 4, 2005
Revision A10