W925E625 Datasheet, PDF (33/75 Pages) Winbond – 8-bit CID MICROCONTROLLER

W925E/C625
6.4 Instruction
The W925E/C625 executes all the instructions of the standard 8032 family. However, timing of these
instructions is different. In the W925E/C625, each machine cycle consists of 4 clock periods, while in
the standard 8032 it consists of 12 clock periods. Also, in the W925E/C625 there is only one fetch per
machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine
cycle, which works out to 6 clocks per fetch.
Table 2 Instructions that affect Flag settings
INSTRUCTION CARRY
INC,DEC
-
ADD
X
ADDC
X
SUBB
X
MUL
0
DIV
0
DA A
X
RRC A
X
RLC A
X
AUXILIARY
OVERFLOW
INSTRUCTION CARRY OVERFLOW
CARRY
-
-
SETB C
1
X
X
CLR C
0
X
X
CPL C
X
X
X
ANL C, bit
X
X
ANL C, bit
X
X
ORL C, bit
X
ORL C, bit
X
MOV C, bit
X
CJNE
X
AUXILIARY
CARRY
A “X” indicates that the modification is as per the result of instruction.
A “-“ indicates that the flag is not effected by the instruction.
INSTRUCTION
NOP
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
Table 3 Instruction Timing for W925E/C625
HEX
MACHINE
BYTES
OP-CODE
CYCLES
00
1
1
28
1
1
29
1
1
2A
1
1
2B
1
1
2C
1
1
2D
1
1
2E
1
1
2F
1
1
26
1
1
27
1
1
25
2
2
24
2
2
38
1
1
39
1
1
3A
1
1
3B
1
1
INSTRUCTION
ANL A, R0
ANL A, R1
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
ANL A, @R0
ANL A, @R1
ANL A, direct
ANL A, #data
ANL direct, A
ANL direct, #data
ANL C, bit
ANL C, /bit
CJNE A, direct, rel
HEX
MACHINE
BYTES
OP-CODE
CYCLES
58
1
1
59
1
1
5A
1
1
5B
1
1
5C
1
1
5D
1
1
5E
1
1
5F
1
1
56
1
1
57
1
1
55
2
2
54
2
2
52
2
2
53
3
3
82
2
2
B0
2
2
B5
3
4
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Publication Release Date: July 4, 2005
Revision A10