ISD5216 Datasheet, PDF (47/75 Pages) Winbond – 8 to 16 minutes voice record/playback device with integrated codec

ISD5216
10. Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
11. Power down the internal oscillator—Bit PDOS controls the power up state of the internal
ChipCorder oscillator. This is bit D8 of CFG0 and it should be set to a ONE to power down
this oscillator
12. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN
input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this
stage.
13. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the
SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in
CFG1, and bits D5 and D6 in CFG1, respectively. All four bits should be set to a ONE in order
to power down these two amplifiers.
14. Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage
in the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
15. Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC
amplifier. This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
16. Don’t Care bits—All other bits are not used in Feed Through Mode. Their bits may be set to
either level. In this example, we will set all the "Don’t Care" bits to a ZERO.
This setup should result in the following configuration register values:
CFG0=0010 0101 0100 1011 (hex 254B)
CFG1=0000 0001 1110 0011 (hex 01E3).
CFG2=0000 0000 0100 0000 (hex 0040).
The three registers must be loaded with CFG0 first followed by CFG1 and CFG2. The internal set up
for these registers will take effect synchronously, with the rising edge of SCL.
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Publication Release Date: Jan. 31, 2006
Revision B.4