ISD5216 Datasheet, PDF (13/75 Pages) Winbond – 8 to 16 minutes voice record/playback device with integrated codec

ISD5216
7.2.2. Digital Input to Analog Output Path
The digital input interface must be selected to either PCM or I²S using the interface selector bit (I²S0)
in the configuration register. The compression format must also be selected with bits (LAW1 – LAW0)
in the configuration registers.
The external clock input signal on pin MCLK and the internal clock dividers must be set to values
supporting the selected digital input signal.
The digital smoothing and interpolation filter runs at 3.4 kHz and feeds the ΣΔ D/A converter that can
be switched off to conserve power and reduce noise using the D/A power down bit (DAPD).
The analog output amplifier gain is controlled from configuration registers bits (COG2 – COG0) from -
8 dB to +6 dB.
7.2.3. CODEC External Clock Configuration
The ISD5216 has two Master Clock configuration bits that allow four possible Master Clock
frequencies. Bits CKD2 and CKDV set the Master Clock Division ratios. These are bits D12 and D8 of
CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also set the
CODEC sample frequency as shown in the following table.
Master Clock Possible Settings
F_MCLK
13.824 MHz
20.48 MHz
27.648 MHz
40.96 MHz
13.824 MHz
20.48 MHz
27.648 MHz
40.96 MHz
*not tested
HSR0 (D5)
(CFG2)
0
0
0
0
1
1
1
1
CKD2 (D12)
(CFG2)
0
0
1
1
0
0
1
1
CKDV (D8)
(CFG2)
0
1
0
1
0
1
0
1
F_SCODEC
8 kHz
11.852 kHz*
8 kHz
11.852 kHz*
32 kHz*
44.1 - 48 kHz
32 kHz*
44.1-48 kHz
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Publication Release Date: Jan. 31, 2006
Revision B.4