ISD5216 Datasheet, PDF (11/75 Pages) Winbond – 8 to 16 minutes voice record/playback device with integrated codec

ISD5216
7.1. MEMORY ORGANIZATION
The ISD5216 memory array is arranged as 1888 rows (or pages) of 2048 bits, for a total memory of
3,866,624 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in
the analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus, at 8
kHz there is actually room for 8 minutes and 3 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage.
The contents of a page are either analog or digital. This is determined by instruction (op code) at the
time the data is written. A record of what is analog and what is digital, and where, is stored by the
system microcontroller in the message address table (MAT). The MAT is a table kept in the
microcontroller memory that defines the status of each message “block.” It can be stored back into the
ISD5216 if the power fails or the system is turned off. Use of this table allows for efficient message
management. Segments of messages can be stored wherever there is available space in the
memory array.
When a page is used for analog storage, the same 32 blocks are present, but there are 8 EOM (End-
of-Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus,
when recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when
the Stop command is issued, but continues until the 32-millisecond block is filled. Then a bit is placed
into the EOM memory to develop the interrupt that signals a message is finished playing in the
Playback mode.
Digital data is sent and received, serially, over the I²C interface. The data is serial-to-parallel
converted and stored in one of two alternating (commutating) 64-bit shift registers. When an input
register is full, it becomes the register that is parallel written into the array. The prior write register
becomes the new serial input register. A mechanism is built in to ensure there is always a register
available for storing new data.
Storing data in the memory is accomplished by accepting data, one byte at a time, and issuing an
acknowledgement. If data is coming in faster than it can be written, then the chip will not issue an
acknowledgement to the host microcontroller until it is ready.
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
array and serially sent to the I²C port. (See Digital Mode on page 26 for details).
7.2. CODEC
The CODEC built into the ISD5216 supports both the I²S and PCM digital interface using μ-Law and
A-Law companding as well as 2’s complement and signed magnitude data. The CODEC meets the
PCM conformance specification of the G.714 recommendation. Its μ-Law and A-Law compander
meets the specification of the ITU-T G.711 recommendation.
The CODEC operates in full duplex in PCM mode and half duplex in I²S mode. Operating the CODEC
requires an external master clock running at 13.824 MHz, 20.48 MHz, 27.648 MHz or 40.96 MHz. This
provides a sampling frequency ranging from 8kHz to 48kHz.
- 11 -
Publication Release Date: Jan. 31, 2006
Revision B.4