ISD5216 Datasheet, PDF (17/75 Pages) Winbond – 8 to 16 minutes voice record/playback device with integrated codec

ISD5216
7.3.5. Additional ISD5216 flow control
The I²C Interface in the ISD5216 differs from the standard implementation in the way the SCL line is
also used for flow control. The ISD5216 will hold the clock line low until it is ready to accept another
command/data. The SCL line must be implemented as a bi-directional line like the SDA line.
For example, the sequence of sending the slave address will be as follows:
1. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
2. Wait for slave to acknowledge (ACK)
3. Next time the clock is pulled high by the master, wait for SCL to actually go high.
7.3.6. I²C Protocol Addressing
Since the I²C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit
that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master.
Before any data is transmitted on the I²C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1^st byte following the
Start Condition sequence. An example of a Master transmitting an address to a ISD5216 slave is
shown below. In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits.
Master Transmits to Slave Receiver (Write) Mode
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S SLAVE ADDRESS W A
COMMAND BYTE
A
High ADDR. BYTE
A
Low ADDR. BYTE
AP
Start Bit
R/W
Stop Bit
A common procedure in the ISD5216 is the reading of the Status Bytes. The Read Status condition in
the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address,
immediately followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an
example of the Master sending to the Slave, immediately followed by the Slave sending data back to
the Master. The “N” not-acknowledge cycle from the Master ends the transfer of data from the Slave.
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Publication Release Date: Jan. 31, 2006
Revision B.4