ISD5216 Datasheet, PDF (21/75 Pages) Winbond – 8 to 16 minutes voice record/playback device with integrated codec

ISD5216
transmitting data that is synchronized with the leading edge (see the timing specifications at the back
of this data sheet).
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
7.4.2. Word Select
The word select line indicates the channel being transmitted:
• WS = 0; channel 1 (left)
• WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be
symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line
changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive
synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the
receiver to store the previous word and clear the input for the next word (see figure Timing for I²S
Transmitter on previous page.)
7.4.3. Timing
In the I²S format, any device can act as the system master by providing the necessary clock signals. A
slave will usually derive its internal clock signal from an external clock input. This means, taking into
account the propagation delays between master clock and the data and/or word-select signals, the
total delay is simply the sum of:
• the delay between the external (master) clock and the slave’s internal clock; and
• the delay between the internal clock and the data and/or word-select signals.
For data and word-select inputs, the external to internal clock delay is of no consequence because it
only lengthens the effective set-up time (see figure Timing for I²S Transmitter on previous page.) The
major part of the time margin is to accommodate the difference between the propagation delay of the
transmitter, and the time required to set up the receiver.
All timing requirements are specified relative to the clock period or to the minimum allowed clock
period of a device. This means that higher data rates can be used in the future.
Timing for I²S Receiver
SCK
SD
and
WS
T
t_LC > 0.35T
t_ar > 0.2T
t_HC > 0.35
t_ar > 0
V_H = 2.0V
V_L = 0.8V
T = clock period
T_R = minimum allowed clock period for transmitter
T > T_R
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
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Publication Release Date: Jan. 31, 2006
Revision B.4