W9816G6IH_10 Datasheet, PDF (40/42 Pages) Winbond – 512K × 2 BANKS × 16 BITS SDRAM

W9816G6IH
11.22 CKE/DQM Input Timing (Read Cycle)
CLK cycle No. ¹
2
CLK
External
Internal
CKE
DQM
DQ
Q1
Q2
CLK cycle No. ¹
2
CLK
External
Internal
CKE
DQM
DQ
Q1
Q2
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
Q1
Q2
3
4
5
6
7
Q3
Q4
(1)
3
4
Q6
Open
Open
5
6
7
Q3
Q4
(2)
3
4
5
Q6
Open
6
7
Q3
Q4
Q5
Q6
(3)
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Publication Release Date: Mar. 22, 2010
Revision A02