W9816G6IH_10 Datasheet, PDF (19/42 Pages) Winbond – 512K × 2 BANKS × 16 BITS SDRAM

W9816G6IH
10.3 Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMH
tCMS
t CMH
tCMS
DQM
DQ0 -15
tDS
t DH
Valid
Data-in
(Clock Mask)
CLK
t CKH
tDS
t DH
Valid
Data-in
tCKS
t CKH
tCKS
CKE
DQ0 -15
tDS
tDH
Valid
Data-in
tDS
t DH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
t DH
Valid
Data-in
Control Timing of Output Data
(Output Enable)
CLK
t CMH
t CMS
t CMH
DQM
DQ0 -15
(Clock Mask)
t AC
t OH
t AC
tOH
Valid
Data-Out
CLK
t CKH
tCKS
tCKH
CKE
DQ0 -15
tAC
t OH
tAC
t OH
Valid
Data-Out
tCMS
tHZ
t OH
Valid
Data-Out
tAC
tLZ
OPEN
tCKS
Valid
Data-Out
tAC
tOH
tAC
tOH
Valid
Data-Out
t AC
t OH
Valid
Data-Out
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Publication Release Date: Mar. 22, 2010
Revision A02