W9816G6IH_10 Datasheet, PDF (38/42 Pages) Winbond – 512K × 2 BANKS × 16 BITS SDRAM

W9816G6IH
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10 11
(1) Read cycle
( a ) CAS latency =2
Command Read
BST
DQ
( b )CAS latency = 3
Command
Read
DQ
Q0 Q1 Q2 Q3 Q4
BST
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
Command Write
BST
DQ Q0 Q1 Q2 Q3 Q4
Note: BST represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
(1) R ead cycle
(a) C A S latency = 2
C om m and
DQ
(b) C A S latency = 3
C om m and
DQ
Read
Read
PRCG
Q0
Q1
Q2
Q3
Q4
PRCG
Q0
Q1
Q2
Q3
Q4
9 10 11
(2) W rite cycle
C om m and
W rite
PRCG
tW R
DQM
DQ
Q0
Q1
Q2
Q3
Q4
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Publication Release Date: Mar. 22, 2010
Revision A02