W986432AH Datasheet, PDF (38/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

Timing Chart of Burst Stop Cycle (Burst Stop Command)
W986432AH
0 1 2 3 4 5 6 7 8 9 10 11
(3) Read cycle
( a ) CAS latency =2
Command Read
BST
DQ
( b ) CAS latency = 3
Command
Read
Q0 Q1 Q2 Q3 Q4
BST
DQ
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
Command Write
BST
DQ D0 D1 D2 D3 D4
Note: BST
represents the Burst stop command
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