W986432AH Datasheet, PDF (2/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

W986432AH
PIN DESCRIPTION
PIN NAME
A0−A10
BS0, BS1
DQ0−DQ31
CS
RAS
CAS
WE
DQM0−
DQM3
CLK
CKE
VCC
VSS
VCCQ
VSSQ
NC
FUNCTION
DESCRIPTION
Address
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
Bank Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Data Input/
Output
Multiplexed pins for data output and input.
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock RAS , CAS and WE define the operation to be
executed.
Column Address _{Referred to RAS}
Strobe
Write Enable
Referred to RAS
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) for Separated power from VCC, to improve DQ noise immunity.
I/O buffer
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise immunity.
No Connection No connection
-2-