W986432AH Datasheet, PDF (17/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

W986432AH
Control Timing of Input Data
(Word Mask)
CLK
tCMH
DQM0
DQM1
DQ0 -DQ7
DQ8-DQ15
DQ16 -DQ23
DQ24-DQ31
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCMS
tCMH
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCMS
tCMH
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
(Clock Mask)
CLK
tCKH
CKE
DQ0 -DQ7
DQ8 -DQ15
DQ16 -DQ23
DQ24 -DQ31
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCKS
tCKH
tCKS
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCMS
tCMH
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tCMS
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
*DQM2,3="L"
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
- 17 -
Publication Release Date: December 1999
Revision A1