W986432AH Datasheet, PDF (36/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

W986432AH
Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0 D1 D2 D3
( b ) Command
DQM
DQ
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Read
Write
D0 D1 D2 D3
Read Write
D0 D1 D2 D3
Read
Write
D0 D1 D2 D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
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