W986432AH Datasheet, PDF (12/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

W986432AH
AC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6, 7, 11)
PARAMETER
-55
-6
-7
-8
UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command Period tRC 60
60
70
72
nS
9
Active to precharge Command Period
tRAS 38.5 100000 42 100000 48 100000 48 100000
9
Active to Read/Write Command Delay Time tRCD 16.5
18
20
20
9
Read/Write(a) to Read/Write(b)Command tCCD 1
Period
1
1
1
Cycle 9
Precharge to Active(b) Command Period
Active(a) to Active(b) Command Period
tRP 18
tRPD 11
18
20
20
12
14
16
nS
9
9
Write Recovery Time
CL* = 2 tWR 10
10
10
10
CL* = 3
5.5
6
7
8
CLK Cycle Time
CL* = 2 tCK 10 1000 10 1000 10 1000 10 1000
CL* = 3
5.5 1000 6 1000 7 1000 8 1000
CLK High Level
CLK Low Level
tCH 2
2.5
3
3
10
tCL 2
2.5
3
3
10
Access Time from CLK
CL* = 2 tAC
7
CL* = 3
5
7
7
7
5.5
5.5
6
Output Data Hold Time
tOH 2
2
2.5
3
Output Data High Impedance Time
tHZ 2
5.5
2
6 2.5 7
3
8
8
Output Data Low Impedance Time
tLZ 0
0
0
0
Power Down Mode Entry Time
tSB 0
5.5
0
6
0
7
0
8
Transition Time of CLK (Rise and Fall)
Data-in-Set-up Time
tT 0.3 10 0.3 10 0.3 10 0.3 10
tDS 1.5
2
2
2
Data-in Hold Time
tDH 1
1
1
1
Address Set-up Time
Address Hold Time
tAS 1.5
2
2
2
tAH 1
1
1
1
CKE Set-up Time
tCKS 1.5
2
2
2
CKE Hold Time
Command Set-up Time
tCKH 1
1
1
1
tCMS 1.5
2
2
2
Command Hold Time
tCMH 1
1
1
1
Refresh Time
Mode Register Set Cycle Time
tREF
64
64
64
64 mS
tRSC 11
12
14
16
nS
9
- 12 -