W986432AH Datasheet, PDF (37/44 Pages) Winbond – 512K x 4 BANKS x 32 BITS SDRAM

W986432AH
Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
01 ^{2 3 4 5 6 7 8 9}
(1) CAS Latency = 2
( a ) Command
DQM
DQ
Write Read
D0
Q0 Q1 Q2 Q3
( b ) Command
DQM
DQ
Write
Read
D0 D1
Q0 Q1 Q2 Q3
10 11
(2) CAS Latency = 3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Write Read
D0
Write
Read
D0 D1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
- 37 -
Publication Release Date: December 1999
Revision A1