W83L784R_05 Datasheet, PDF (37/52 Pages) Winbond – Monitoring IC

W83L784R/ W83L784G
7.29 FAN 1 Duty Cycle Select Register -- 81h (Bank 0)
Power on default [7:0] 1111, 1111 b
BIT
NAME
7-0 F1_DC[7:0]
READ/WRITE
Read/Write
DESCRIPTION
Fan 1 Duty Cycle. This 8-bit register determines the
number of input clock cycles, out of 256-cycle period,
during which the PWM output is high. During smart fan
1 control mode, read this register will return smart fan
duty cycle.
00h: PWM output is always logical Low.
FFh: PWM output is always logical High.
XXh: PWM output logical High percentage is
(XX/256*100%) during one cycle.
7.30 FAN 2 Pre-Scale Register -- Index 82h
Power on default [7:0] = 0000, 0001 b
BIT
NAME
READ/WRITE
DESCRIPTION
7 PWM_CLK_SEL2 Read/Write
PWM 2 Input Clock Select. This bit select Fan 2 input
clock to pre-scale divider.
0: 1 MHz
1: 125 KHz
6-0 PRE_SCALE2[6:0] Read/Write
Fan 2 Input Clock Pre-Scale. The divider of input
clock is the number defined by pre-scale. Thus, writing
0 transfers the input clock directly to counter. The
maximum divider is 128 (7Fh).
00h : divider is 1
01h : divider is 2
02h : divider is 3
:
:
7.31 FAN2 Duty Cycle Select Register -- Index 83h
Power on default [7:0] = 1111, 1111 b
BIT
NAME
7-0 F2_DC[7:0]
READ/WRITE
Read/Write
DESCRIPTION
Fan 2 Duty Cycle. This 8-bit register determines the
number of input clock cycles, out of 256-cycle period,
during which the PWM output is high. During smart fan
2 control mode, read this register will return smart fan
duty cycle.
00h: PWM output is always logical Low.
FFh: PWM output is always logical High.
XXh: PWM output logical High percentage is
XX/256*100% during one cycle.
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Publication Release Date: Jan. 2005
Revision 1.1