W963L6ABN Datasheet, PDF (26/30 Pages) Winbond – 512K WORD X 16 BIT LOW POWER PSEUDO SRAM

W963L6ABN
Timing Waveforms, Continued
Power-up Timing #2
CE1
CE2
VDD
0V
tC2HL
tCSP
tC2HL
VDD min
tC2LP
tCHS
tCHH
Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level.
CE1 must be brought to High prior to or together with CE2 Low to High transition.
Standby Entry Timing after Read or Write
CE1
OE
WE
tCHOX
Active (Read)
Standby
tCHWX
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min)
period from either last address transition of A0, A1 and A2, or CE1 Low to High transition.
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