VSC6511 Datasheet, PDF (17/22 Pages) Vitesse Semiconductor Corporation – SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
Pin #
30
26
34
27
25
21,22
56,54
60,58
52,62
53,61
29
31
33
16,17
49,19
1
20,23,28,57,51
5,10,39,44
63
18
55,59
14,32,35,48
15
Name
Description
BIDIRECTIONAL - TTL: In Serializer Mode, CRC Generation is enabled when
CRC
this input is HIGH and disabled when LOW. In Deserializer Mode and
Deserializer/Reclocker Mode, this is an output which indicates a CRC error has
occurred.
FRAME
LINE
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a FRAME synchronization event is on
D[0:19].
OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an
output which, when HIGH, indicates that a LINE synchronization event is on
D[0:19].
HANC
OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period
between EAV and SAV.
1.001
OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on
SDI/SDI and that the SMPTE-292M incoming data is greater than 500ppm from
20xREFCLK.
SDI, SDI INPUT - Differential. Serial input to CRU.
SDO0, SDO0 OUTPUT - Differential. High Speed Cable Driver output.
SDO1, SDO1 Serial output from the Serializer, Reclocker or SDI/SDI input buffer.
ISET0, ISET1
OE0, OE1
REFCLK
RCLK
Connect resistor to ground to set the output swing of SDO0, and SDO1
INPUT - TTL. Output enable pins for SDO0, and SDO1. Enabled when high for
each output.
INPUT - TTL. REFerence CLocK at 74.25 MHz. This is the input to the CMU and
times D(19:0) in Serializer Mode.
OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered
version of REFCLK. In Deserializer Mode, this is the recovered clock used to time
D(19:0).
SIGDET
OUTPUT - TTL. An analog signal detect output which, when HIGH, indicates
that the IP/IN input contains a valid SMPTE-292M amplitude signal.
CAP0, CAP1 Analog I/O: Loop Filter Capacitor, 0.1uF nominal, 3V swing maximum
TEST1, TEST2 INPUT - TTL. LOW for factory test, HIGH for normal operation.
INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance is
V53
required, this pin should be connected to 5V supply.
VDDD Power Supply. 3.3V Supply for digital logic.
VDDT
VREF
TTL I/O Power Supply.
Voltage Reference Input. If used, this is biased to 1.25V.
VDDA Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15.
VSSP
VSST
Ground for High Speed Outputs
TTL I/O Ground
VSSA Analog Ground Bypass to pin 18.
G52311-0, Rev. 2.0
4/10/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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